ABOUT ANTI-TAMPER DIGITAL CLOCKS

About Anti-Tamper Digital Clocks

About Anti-Tamper Digital Clocks

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30. An equipment for detecting voltage tampering, comprising: indicates for supplying a steady-state monotone signal in the course of an Appraise period of time;

Resettable hold off line segments amongst a resettable delay line phase 210-1 connected to a minimum hold off time as well as a resettable hold off line segment 210-N associated with a most delay time are Just about every associated with discretely growing delay occasions. The Assess circuit 240 is induced because of the clock CLK and uses the plurality of delayed monotone indicators to detect a clock fault.

In other more specific areas of the invention, Each individual of your plurality of delayed monotone indicators 230 might be either a a person or possibly a zero. The Consider circuit 240 may identify no matter if the quantity of kinds during the plurality of delayed monotone signals differs from a drinking water level number by much more than a predetermined threshold.

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37. An equipment for detecting voltage tampering, comprising: a circuit that gives a monotone sign all through an Appraise time frame;

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An additional aspect of the creation could reside in an apparatus for detecting clock tampering, comprising: usually means 250 for giving a monotone signal 220 during a clock Examine time period 310 connected to a clock CLK; suggests 210 for delaying the monotone signal utilizing a plurality of resettable hold off line segments to create a respective plurality of delayed monotone alerts 230 possessing discretely growing delay situations amongst a minimum delay time and also a optimum hold off time; and implies 240 for utilizing the clock CLK to cause an Appraise circuit 240 that makes read more use of the plurality of delayed monotone indicators to detect a clock fault.

an Assess circuit, induced by a clock, that makes use of the plurality of delayed monotone signals to detect a voltage fault.

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